1. Field of the Invention
This invention pertains to surface mount devices generally, and specifically to surface mount resistor networks.
2. Description of the Related Art
High quality resistor networks are typically made from ceramic substrates which have patterned thereon ceramic-metal composite conductors. These cermet conductors are fired at elevated temperatures, typically 800.degree.-1000.degree. C. The thusly formed cermet resistors have performance characteristics which are significantly better than lower temperature polymeric resistor materials. However, the elevated firing temperature does necessitate the use of ceramic substrates.
Due to local heating of a resistor element, sudden changes in the ambient or other causes, a finished and mounted resistor network will rarely always see the same temperature and rate of temperature change as the wiring substrate that the network is attached to. Such variances result in differing expansion and contraction, which will produce stresses between the network and the substrate. Those thermally induced stresses can result in interconnection failure if not properly relieved. In the prior art, such stresses were readily relieved by elastic deformation of the lead wires of the resistor network. However, this type of stress relief is not available in those instances where the manufacturer has required surface mount devices where there is not adequate space for lead wires. This lack of stress relief is emphasized in those instances where the application requires the performance characteristics best obtainable with unyielding ceramic substrates and cermet conductors and resistors. Therefore some other way must be found to solve thermal stress problems if the manufacturer is still going to be able to take for granted the quality available from cermet resistors and yet design high speed, densely packed circuitry.
As modern electronic devices become faster and more densely packed, there is a continuing trend towards the attachment of devices with little if any electrical wire intermediary to the device and a substrate. Generally, any wiring will be present only on or within the substrate and extra wire extending from a component may be regarded as being deleterious to performance, packaging density, and suitability for multi-layer printed wiring boards. This is because the wire introduces additional connections between the component and the board (component to wire to board as opposed to component to board) which reduces the overall reliability somewhat. The wire additionally requires a finite amount of space which reduces packing density and which in high speed circuitry may introduce signal propagation delay and noise and signal degradation. Additionally, the wire may require additional holes through the circuit board for mounting each termination. The through holes that are required must be drilled through each layer of the circuit board and therefore require vacancies in the wiring pattern which complicates wiring layout.
Unfortunately, where a different resistor substrate material is used from that of the wiring substrate, or where the resistor substrate is thermally remote from the wiring substrate, differences in expansion and contraction are often emphasized sufficiently that failure does occur in the interconnection between the resistor network and the wiring substrate.
Some of the prior art attempts at overcoming this mechanism of failure have included attaching a miniature lead-frame from the bottom of the resistor to the wiring board, or in another device, wrapping a lead-frame entirely around the device and encapsulating the device in plastic. The plastic and lead-frame are much more resilient than the ceramic resistor substrate and will in many cases suffice to prevent disruption of the interconnection between the resistors and the wiring substrate.
However, the assembly of the resistor network is complicated very much by the incorporation of the lead-frame, making the finished device more expensive to produce. Additionally, the application of this technology to smaller production quantities becomes entirely cost prohibitive and the space for this technology may not exist at all as designs become progressively smaller.
Related technologies such as chip resistor and chip capacitor design have in the past included features to prevent failure of the device interconnection to the wiring substrate. One known method is to form a solder fillet between the chip and the wiring substrate of a particular shape which reduces the stress within the solder at any one point to a minimum. In this way, the solder is able to accommodate stresses by slight elastic deformation through the normal temperature excursions which the wiring substrate and the chip would be exposed. However, there has heretofore not been any economical application of chip technology to resistor networks, presumably for several reasons.
The first of these reasons is the increased overall dimension of a resistor network. The chip merely requires the printing of two terminations and one resistor between those two terminations. In the case of a resistor network, there is typically more than one external termination for every resistor printed upon the network substrate. This may run to twenty or more terminations on occasion. The increased dimension necessitated by the multiple terminations translates into greater actual differences in dimensional changes between the network and the wiring substrate with changes in temperature.
A second reason for the lack of application of the chip technology to resistor networks stems from the numbers of total terminations and the relative proximity of those terminations one to another. With a chip resistor, significant misalignment between the chip and the wiring substrate does not affect the interconnection integrity. However, where there are multiple terminations spread across a greater total dimension, alignment becomes much more critical. This may be further aggravated by manufacturing tolerances on the locations of the terminations. Generally, wire terminations may be used to compensate for misalignment and manufacturing tolerances, whereas a chip type design does not require nor incorporate any feature to accommodate this type of problem.